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Apple and Qualcomm have quietly signaled interest in Intel’s advanced packaging tech, according to recent job listings. As chip designers hunt for ways to boost performance and capacity, Intel’s EMIB and Foveros are suddenly getting a lot of attention — and that attention could reshape the competitive landscape for advanced packaging and foundry services.
Why big tech is looking past Moore’s Law
Moore’s Law no longer delivers the same easy gains it once did, so the industry has leaned heavily on advanced packaging to stack, stitch, and scale chips inside a single package. Technologies that let companies combine multiple chiplets or stack dies have become central to high-performance computing designs from Nvidia, AMD, and custom silicon teams at Apple and Qualcomm.
For years, TSMC dominated this segment with offerings like CoWoS, but surging demand from major GPU and CPU customers has created capacity pressure. That bottleneck has opened a window for alternative suppliers — and Intel is stepping into that gap.
EMIB and Foveros: two different routes to denser chips
Intel’s EMIB, or Embedded Multi-Die Interconnect Bridge, uses tiny silicon bridges to link multiple chiplets within one package without the need for a large interposer. The result can be lower cost and greater design flexibility for multi-die systems.
Foveros takes a complementary approach: die stacking. By using through-silicon vias (TSVs) and fine-pitch vertical integration, Foveros lets designers stack logic and memory vertically for tighter integration and reduced latency. Both methods are attractive to companies that want the benefits of heterogeneous integration without being fully tied to one foundry’s packaging roadmap.
Clues from recruitment: Apple and Qualcomm job postings
Recently surfaced job listings from Apple and Qualcomm mention experience with Intel’s EMIB and other packaging technologies. Apple’s opening for a DRAM packaging engineer lists CoWoS, EMIB, SoIC, and PoP in its requirements. Qualcomm’s listing for a director of product management in its data center unit also flags EMIB familiarity.
Job postings don’t equal contracts, but they’re a strong indicator that engineering teams are at least evaluating Intel’s stack. When two industry heavyweights explicitly ask for knowledge of the same Intel technology, it suggests active exploration rather than passive curiosity.
What this could mean for the foundry market
If Apple, Qualcomm, or other major designers choose Intel for advanced packaging, the implications are significant. First, it would confirm that Intel’s ecosystem is mature enough to support leading-edge, custom silicon programs. Second, it would ease pressure on TSMC’s constrained advanced packaging lines, giving designers more negotiating power and scheduling flexibility.
Nvidia CEO Jensen Huang has publicly praised Foveros in the past, a nod that adds credibility to Intel’s solutions. Whether that praise translates into commercial volume is another question, but it does highlight that top designers see the technical promise in Intel’s approach.
What to watch next
- New partnerships or wafer- or package-level supply agreements between Intel and major designers.
- Announcements of product designs that explicitly list EMIB or Foveros in their packaging notes.
- TSMC capacity moves — any expansion or prioritization changes will shift how quickly customers diversify.
Advanced packaging has become an axis of competition as much as process nodes and transistor density. Intel’s EMIB and Foveros are no silver bullets, but they are credible alternatives. As chipmakers push performance limits by combining chiplets and stacked dies, engineering hires and quiet evaluations often foreshadow a bigger strategic shift. Keep an eye on future job listings, partnership announcements, and product teardowns to see whether Intel’s packaging becomes a mainstream option for the next wave of custom silicon.
Source: wccftech
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