Why Google Is Turning to AMD for Its TPU v10 Chips

Picture a future Google data center where bespoke AI accelerators sit shoulder-to-shoulder with high-performance AMD cores. Strange? Perhaps. Strategic? Absolutely.

Market whispers that surfaced in a SemiAnalysis note say Google is working with AMD on one of the models in its tenth-generation TPU family. If true, this would be AMD’s first major foray into a custom AI ASIC project at this scale. The idea isn’t to hand over the whole TPU blueprint to a chipmaker; it’s to fold AMD’s IP and packaging expertise into a hybrid architecture that can handle a new class of workloads.

This would mark AMD's first major custom AI chip partnership with Google.

Why bring AMD into the ring now? The answer lies in how AI is evolving. Modern models increasingly demand more than sheer matrix math. They need versatile general-purpose processing alongside accelerators — think reinforcement learning loops, operating-system-level orchestration, and complex reasoning tasks that can’t be offloaded entirely to tensor engines. Embedding AMD CPU cores directly on the TPU package would give Google the flexibility to run those mixed workloads with lower latency and tighter integration.

AMD’s strengths are clear: advanced packaging technologies like SoIC, a deep patent portfolio, and mature CPU architectures. Those assets matter when you’re stacking dies, routing high-bandwidth links, and trying to squeeze every ounce of performance and power efficiency out of a single package. Google already designs much of its accelerator architecture and has historically partnered with Broadcom for earlier TPU generations. This time, however, the play looks like a marriage of custom accelerators and a heavyweight CPU supplier.

Don’t expect AMD to be retasked as the chief architect for TPU inference or training variants. The smarter bet is that Google needs programmable logic blocks, bespoke interconnects, and packaging know-how that a major CPU vendor can deliver — things that go beyond plain accelerator design. In practice, that means hybrid chips where specialized tensor engines coexist with general-purpose cores that handle control, scheduling, and the messy bits of real-world AI workloads.

There are precedents in Google’s server evolution. Recent TPU 8i deployments pair accelerators with Google’s own Axion processor, while older setups relied on Intel Xeon CPUs shared across multiple accelerators. The trend over generations has been toward more local processing muscle per accelerator — a hint at why integrating AMD cores could be attractive.

For cloud customers, the implications are practical: fewer cross-chip hops, better throughput for reinforcement-learning pipelines, and potentially new deployment patterns for latency-sensitive services. For AMD, it’s a chance to show packaging and heterogeneous-integration chops in an arena long dominated by bespoke ASIC teams.

Either way, this partnership — if finalized — would underline a shift in how hyperscalers think about custom silicon: not just faster matrix math, but tighter ecosystems of diverse compute elements working in concert. Watch this space; the next decade of cloud AI might be built less like a single engine and more like an orchestra tuning up.