Stacked Silicon Chips Could Keep Moore's Law Alive Soon

Room is running out on the flat plane of today's chips. So researchers at the University of Illinois Urbana-Champaign tried the obvious: build up instead of out.

Think of a suburban sprawl replaced by high-rises. Same people, less walking. The team used the same single-crystal silicon found in current processors but rearranged transistors in vertical stacks, shrinking the footprint while shortening the electrical paths that slow and waste energy.

Stacking isn't new. The hurdle has always been heat. Conventional chip fabrication demands temperatures near 1,000 °C, and baking a second layer on top of a finished first layer risks destroying it. Past work tried gluing pre-baked layers together or switching to exotic, heat-tolerant materials—but those routes sacrifice performance, density, or the tight device integration that makes a chip fast.

Here the group sidestepped the oven. They combined two key moves. First: junctionless transistors, which shift the tough, high-temperature engineering steps to before layering. Second: ultra-thin silicon nanomembranes—flexible sheets of single-crystal silicon that can be applied like a film at temperatures below 200 °C. The membranes conform to the surface beneath, avoiding voids and other bonding defects that plague rigid wafer-to-wafer approaches.

The result: monolithic three-dimensional integration that keeps the electrical quality and yields engineers expect from today’s chips, while stacking logic and memory across multiple layers. In experiments the team built functioning circuits and memory cells across three vertically stacked layers—a proof of concept that both validates the approach and suggests room to grow.

This is the first demonstration of meeting the thermal budget for true monolithic 3D integration using standard single-crystalline silicon while delivering competitive performance.

Why does this matter? More transistors in the same volume means more compute density, faster interconnects, and potentially lower energy per operation. That’s the essence of Moore’s Law: pack more transistors into the same cost envelope and performance scales. When horizontal scaling hits a wall, scaling upward offers a clear path to continue improving classical processors.

There are caveats. The stacked devices in the lab currently run at higher-than-normal voltages, a detail that chip designers will want resolved before fabs adopt the method. And scaling a new manufacturing technique from academic clean rooms to commercial foundries always raises questions about yield, throughput, and cost. Still, the researchers report high yields in their trials and say the method can be adapted to industrial processes.

Even as quantum computing chases different kinds of problems, classical silicon devices will remain the backbone of most computing tasks. If monolithic stacking can be industrialized, it could extend the roadmap of transistor scaling without abandoning the silicon ecosystem that powers everything from phones to cloud servers.

Published in Nature, the work feels less like a theoretical detour and more like a practical playbook for chipmakers wondering what comes next. The next chapters will be written in foundries, but the street map is finally in hand.